This invention relates to the manufacture of semiconductor circuit devices. More specifically the invention relates to manufacture of multilayer semiconductor circuit devices in which photomasking steps are used in the manufacture.
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the materials used is silicon, which appears as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
This invention describes a technique to maximize cell capacitor area in a high density/high volume DRAM (dynamic random access memory) fabrication process. It is called "local encroachment reduction" or "LER" for short. The invention is applicable to all high density DRAM planar processes from the 16 Kbit to the 4 Megbit generations and beyond.
It is well known for high density DRAM process/cell design, that maximum cell capacitor active area must be obtained as a percentage of repeating geometry area in a DRAM array. This active region/repeating region ratio determines the overall die size for a given feature size capability. This then translates directly into cost per bit. The active capacitor region must be large enough to insure proper sensing of data by the bitline sense amps and to insure strong immunity to single event upsets such as alpha particles.
One key factor in maximizing cell capacitor active area is in reducing field oxide encroachment into active area during field oxidation. Encroachment can cause a loss of active width up to twice the field ox thickness. As geometries shrink in more advanced generation DRAMs, this effect becomes a dominant factor. A common method of approaching this problem involves use of some sort of field oxidation encroachment reduction technique. Several techniques are discussed in the literature including SWAMI, SILO, BOX, Poly Buffer, Nitrox, trench isolation, and others. Each has their advantages and disadvantages, but all involve adding a great deal of added complexity to the process.
Some prior art processes result in undue crystal stress leading to junction leakage to levels intolerable on DRAM circuits. Others result in large angle abrupt profiles (or even re-entrant profiles in some cases), making anisotropic etch of subsequent thin films difficult. Prior art proposed solutions require a gate oxide strip and regrow (or double strip and regrow) to form the final gate oxide. This has a disadvantage of thinning the field isolation oxide and adds extra process steps. Some of the other methods involve a Si etch into Si substrate, which requires extra precaution during subsequent process steps to avoid generation of stacking faults and other crystal defects.
Other encroachment reduction schemes are more susceptible to isolation leakage due to the reduction in the active area N+ space. Increasing the standard field implant has other performance degradation implications and is therefore not desirable. These degradations include increased N+ junction capacitance and aggravated transistor narrow W effects. The LER approach embodied here suffers from none of the above limitations.
The purpose of this invention is to describe a simple yet extremely effective means of increasing cell capacitor area in an advanced DRAM process called "local encroachment reduction" or "LER". It involves reducing the encroachment of the field ox into the cell active area only locally in the cell active regions. It avoids all the pitfalls of prior art encroachment reduction schemes.